DC-AC conversion is an essential function that exists in every electronic device. More importantly, DC-RF power conversion is a primary function in every transceiver. Modern portable devices, cell phones, tablets, laptops, etc, include many transceivers. Typical transceivers utilize lossy transformers, which tax battery life. The typical transceivers also occupy significant real estate, because a power amplifier is built in a separate chip using expensive non-CMOS (complementary metal-oxide-semiconductor) technology (e.g., heterojunction bipolar transistors (HBT)) and then assembled into the system via difficult and expensive heterogeneous integration techniques.
As CMOS continues to scale, faster devices with better conductance and lower capacitance metrics are realized, and better switching performance is achieved. Scaling produces thinner oxide devices, which saves chip real estate but reduces the voltage blocking breakdown capability of the devices. The capability of such devices to produce high voltage and to pump power into the widely used 50Ω antenna weakens because of the lower voltage blocking capability. This creates difficulties for the monolithic integration of the PA power stage into a digital CMOS chip, and negatively impacts the cost and size reductions. The ability to leverage the huge processing capabilities of CMOS DSPs (digital signal processors) is also compromised.
Conventional circuits and methods make it difficult to efficiently generate high levels of RF power in scaled CMOS largely due to the inherently low voltage ratings of core thin-oxide transistors. To realize high output power with low voltage (˜1V or less) transistors, power combining techniques have been proposed whereby the output of several low-voltage power amplifier (PA) cells are combined via inductive transformers.
This bulky magnetic (non-CMOS compatible) power combining approach that is widely used in the modern RF market was inspired in 2003 by I. Aoki, S. Kee, D. Rutledge, and Ali Hajimiri, [Aoki et al., “Fully Integrated CMOS Power Amplifier Design Using the Distributed Active-Transformer Architecture,” IEEE JSSC, March 2002; Aoki U.S. Pat. No. 6,816,012], which provided a solution for the decreasing CMOS breakdown voltages. The power combining approach introduced by Aoki et al., relies on ultra-thick metal that still carries large ohmic and substrate losses. These AC-AC losses, combined with the DC-AC losses of the power amplifiers (PAs) themselves, and the DC-DC losses of the battery-connected power converters, result in limited total transmitter efficiencies. Even modern digital PA techniques such as RF-DACs, digital Doherty, and digital out-phasing, which have been proposed to leverage the excellent switch performance of scaled transistors and offer reconfigurable operation, still require battery-connected DC-DC converters and RF transformers/power combiners, both of which result in cascaded losses. See, e.g. S.-M. Yoo et al., “A switched-capacitor power amplifier for EER/polar transmitters,” in ISSCC, February 2011, pp. 428-430; S. Hu and et al., “A +27.3 dBm transformer-based digital Doherty polar power amplifier fully integrated in bulk CMOS,” in RFIC, June 2014, pp. 235-238; P. Madoglio et al., “A 20 dBm 2.4 GHz digital outphasing transmitter for WLAN application in 32 nm CMOS,” in IS SCC, February 2012, pp. 168-170.
Modern communication techniques for mobile devices require high-efficiency across a wide dynamic power range. Such techniques include non-constant envelope modulation schemes [e.g., quadrature amplitude modulation (QAM) and Orthogonal frequency division multiplexing (OFDM)], which are important to better utilize allocated bandwidth.
A constellation-points rearrangement has been described to help reduce the peak-to-average power ratio such modulation schemes. See, E. W. McCune, “pPSK for bandwidth and energy efficiency,” in Proc. Eur. Microw. Conf., October 2013, pp. 569-572; E. McCune, “Signal design and figure of merit for green communication links,” in Proc. IEEE Radio Wireless Symp. (RWS), January 2017, pp. 22-25. Such high peak-to-average power ratio (PAPR) signals still require a PA with high efficiency across a wide dynamic power range.
Class-G supply modulation has been demonstrated to achieve high efficiency at back-off by operating a nonlinear PA from multiple supply voltage levels, typically Vin and Vin2, as determined by the input envelope signal in an EER scheme. See, J. S. Walling, S. S. Taylor, and D. J. Allstot, “A class-G supply modulator and class-E PA in 130 nm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2339-2347, September 2009. A second peak at 6-dB back-off in the overall PA efficiency is typically realized by operating the PA from a second supply, Vin/2, when the input signal amplitude (AM) drops below a predetermined threshold. Such a supply modulator can be implemented using a linear voltage regulator. See, e.g., P. Reynaert and M. S. J. Steyaert, “A 1.75-GHz polar modulated CMOS RF power amplifier for GSM-EDGE,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2598-2608, December 2005. Another know alternative is a hybrid design that includes a linear regulator in parallel to a switching supply modulator. See, e.g., “M. Hassan, L. E. Larson, V. W. Leung, and P. M. Asbeck, “A combined series-parallel hybrid envelope amplifier for envelope tracking mobile terminal RF power amplifier applications,” IEEE J. Solid-State Circuits, vol. 47, no. 5, pp. 1185-1198, May 2012. Unfortunately, such approaches require either off-chip or large on-chip inductors for high efficiency. An example dc-dc converter requires two external inductors (4.7 μH and 22 nH) and two external capacitors (0.47 μF and 6.8 nF), and occupies 2.52×2.52 mm2 on chip area to realize an 86.2% dc-dc conversion efficiency at 26.3-dBm output power. See, P. Arno, M. Thomas, V. Molata, and T. Jerabek, “17.6 Envelope modulator for multimode transmitters with AC-coupled multilevel regulators,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, February 2014, pp. 296-297.